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AM3517 Sitara 处理器

数据: AM3517, AM3505 Sitara Processors 数据表

描述

AM3517 /05是一款高性能ARM Cortex-A8微处理器,速度高达600 MHz。该器件提供3D图形加速,同时还支持众多外设,包括DDR2,CAN,EMAC和USB OTG PHY,非常适合工业应用。

该处理器可支持其他应用,包括:单板计算机家庭和工业自动化人机界面

该设备支持高级操作系统(OS),例如:

  • Linux ® < /li>
  • Windows ® CE
  • Android™

以下子系统是设备的一部分:

< ul>
  • 基于ARM Cortex-A8微处理器的微处理器单元(MPU)子系统
  • PowerVR SGX图形加速器(仅限AM3517设备)子系统,用于支持显示和游戏效果的3D图形加速
  • 具有多个功能的显示子系统,用于多个并发图像处理,以及支持各种显示的可编程接口。显示子系统还支持NTSC /PAL视频输出。
  • 高性能互连为多个启动器提供高带宽数据传输,用于内部和外部存储器控制器以及片上外设。该器件还提供全面的时钟管理方案。

AM3517 /05器件采用491引脚BGA封装和484引脚PBGA封装。

该AM3517 /05数据手册介绍了AM3517 /05 Sitara处理器的电气和机械规格。

特性

  • AM3517/05 Sitara Processor:
    • MPU Subsystem
      • 600-MHz Sitara ARM Cortex-A8 Core
      • NEON SIMD Coprocessor and Vector
        Floating-Point (FP) Coprocessor
    • Memory Interfaces:
      • 166-MHz 16- and 32-Bit mDDR/DDR2
        Interface with 1GB of Total Addressable
        Space
      • Up to 83 MHz General-Purpose Memory
        Interface Supporting 16-Bit-Wide
        Multiplexed Address/DataBus
      • 64KB of SRAM
      • 3 Removable Media Interfaces
        [MMC/SD/SDIO]
    • IO Voltage:
      • mDDR/DDR2 IOs: 1.8V
      • Other IOs: 1.8V and 3.3V
    • Core Voltage: 1.2V
    • Commercial and Extended Temperature Grade
      (operating restrictions apply)
    • 16-Bit Video Input Port Capable of
      Capturing HD Video
    • HD Resolution Display Subsystem
    • Serial Communication
      • High-End CAN Controller
      • 10/100 Mbit Ethernet MAC
      • USB OTG Subsystem with Standard
        DP/DM Interface [HS/FS/LS]
      • Multiport USB Host Subsystem [HS/FS/LS]
        • 12-Pin ULPI or 6-, 4-, or 3-Pin Serial
          Interface
      • Four Master and Slave Multichannel Serial
        Port Interface(McSPI) Ports
      • Five Multichannel Buffered Serial Ports (McBSPs)
        • 512-Byte Transmit and Receive Buffer
          (McBSP1/3/4/5)
        • 5-KB Transmit and Receive Buffer (McBSP2)
        • SIDETONE Core Support (McBSP2 and
          McBSP3 Only)For Filter, Gain, and Mix
          Operations
        • 128-Channel Transmit and Receive Mode
        • Direct Interface to I2S and PCM Device and
          TDM Buses
      • HDQ/1-Wire Interface
      • 4 UARTs (One with Infrared Data Association
        [IrDA] and Consumer Infrared [CIR] Modes)
      • 3 Master and Slave High-Speed Inter-Integrated
        Circuit (I2C) Controllers
      • Twelve 32-bit General-Purpose Timers
      • One 32-bit Watchdog Timer
      • One 32-bit 32-kHz Sync Timer
      • Up to 186 General-Purpose I/O (GPIO) Pins
  • Display Subsystem
    • Parallel Digital Output
    • Up to 24-Bit RGB
    • Supports Up to 2 LCD Panels
    • Support for Remote Frame Buffer Interface (RFBI)
      LCD Panels
    • Two 10-Bit Digital-to-Analog Converters (DACs)
      Supporting
      • Composite NTSC/PAL Video
      • Luma/Chroma Separate Video (S-Video)
    • Rotation of 90, 180, and 270 Degrees
    • Resize Images From 1/4x to 8x
    • Color Space Converter
    • 8-Bit Alpha Blending
  • Video Processing Front End (VPFE) 16-Bit Video Input Port
    • RAW Data Interface
    • 75-MHz Maximum Pixel Clock
    • Supports REC656/CCIR656 Standard
    • Supports YCbCr422 Format (8-Bit or 16-Bit with Discrete
      Horizontal and Vertical Sync Signals)
    • Generates Optical Black Clamping Signals
    • Built-in Digital Clamping and Black Level Compensation
    • 10-Bit to 8-Bit A-law Compression Hardware
    • Supports up to 16K Pixels (Image Size) in Horizontal
      and Vertical Directions
  • System Direct Memory Access (sDMA) Controller (32 Logical
    Channels with Configurable Priority)
  • Comprehensive Power, Reset, and Clock Management
  • ARM Cortex-A8 Memory Architecture
    • ARMv7 Architecture
    • In-Order, Dual-Issue, Superscalar Microprocessor Core
    • ARM NEON Multimedia Architecture
    • Over 2x Performance of ARMv6 SIMD
    • Supports Both Integer and Floating-Point SIMD
    • Jazelle RCT Execution Environment Architecture
    • Dynamic Branch Prediction with Branch Target Address
      Cache, Global History Buffer and 8-Entry Return Stack
    • Embedded Trace Macrocell [ETM] Support for
      Noninvasive Debug
    • 16KB of Instruction Cache (4-Way Set-Associative)
    • 16KB of Data Cache (4-Way Set-Associative)
    • 256KB of L2 Cache
  • PowerVR SGX Graphics Accelerator (AM3517 Only)
    • Tile-Based Architecture Delivering up to 10 MPoly/sec
    • Universal Scalable Shader Engine: Multi-threaded Engine
      Incorporating Pixel and Vertex Shader Functionality
    • Industry Standard API Support: OpenGLES 1.1 and
      2.0, OpenVG1.0
    • Fine-Grained Task Switching, Load Balancing, and
      Power Management
    • Programmable, High-Quality Image Anti-Aliasing
  • Endianess
    • ARM Instructions – Little Endian
    • ARM Data – Configurable
  • SDRC Memory Controller
    • 16- and 32-Bit Memory Controller with 1GB of
      Total Address Space
    • Double Data Rate (DDR2) SDRAM, Mobile Double Data Rate
      (mDDR)SDRAM
    • SDRAM Memory Scheduler (SMS) and Rotation Engine
  • General Purpose Memory Controller (GPMC)
    • 16-Bit-Wide Multiplexed Address/Data Bus
    • Up to 8 Chip-Select Pins with 128MB of Address
      Space per Chip-Select Pin
    • Glueless Interface to NOR Flash, NAND Flash (with ECC
      Hamming Code Calculation), SRAM and Pseudo-SRAM
    • Flexible Asynchronous Protocol Control for Interface
      to Custom Logic (FPGA, CPLD, ASICs, and so forth)
    • Nonmultiplexed Address/Data Mode (Limited 2-KB
      Address Space)
  • Test Interfaces
    • IEEE-1149.1 (JTAG) Boundary-Scan Compatible
    • Embedded Trace Macro Interface (ETM)
  • 65-nm CMOS Technology
  • Packages:
    • 491-Pin BGA (17 x 17, 0.65-mm Pitch)
      [ZCN Suffix]
      with Via Channel Array
      Technology
    • 484-Pin PBGA (23 x 23, 1-mm Pitch)
      [ZER Suffix]

参数 与其它产品相比 AM3x

 
Arm MHz (Max.)
Serial I/O
Graphics Acceleration
EMAC
DRAM
Operating Temperature Range (C)
Approx. Price (US$)
AM3517 AM3505
600     600    
USB
I2C
McBSP
McSPI
UART
CAN    
USB
I2C
McBSP
McSPI
UART
CAN    
1 3D      
10/100     10/100    
DDR2
LPDDR    
DDR2
LPDDR    
-40 to 105
0 to 90    
-40 to 105
0 to 90    
18.37 | 1ku     15.94 | 1ku    

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